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September 2001
FDG6303N
Dual N-Channel, Digital FET
General Description Features
These dual N-Channel logic level enhancement mode 25 V, 0.50 A continuous, 1.5 A peak.
field effect transistors are produced using Fairchild's RDS(ON) = 0.45 @ VGS= 4.5 V,
proprietary, high cell density, DMOS technology. This RDS(ON) =0.60 @ VGS= 2.7 V.
very high density process is especially tailored to
minimize on-state resistance. This device has been Very low level gate drive requirements allowing direct
designed especially for low voltage applications as a operation in 3 V circuits (VGS(th) < 1.5 V).
replacement for bipolar digital transistors and small Gate-Source Zener for ESD ruggedness
signal MOSFETs. (>6kV Human Body Model).
Compact industry standard SC70-6 surface
mount package.
SC70-6 SOT-23 SuperSOTTM -6 SuperSOTTM -8 SO-8 SOT-223
S2 1 or 4 *
G2 6 or 3
D1 .03
2 or 5 5 or 2
D2
G1
S1 4 or 1 *
SC70-6
3 or 6
* The pinouts are symmetrical; pin 1 and 4 are interchangeable.
Units inside the carrier can be of either orientation and will not affect the functionality of the device.
Absolute Maximum Ratings TA = 25