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PROPRIETARY INFORMATION THAT IS
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Table of Contents D
Sheet 1. COVER
HABANA-C Sheet 2 - 7. DIAGRAM (Block/Power) & ANNOTATIONS
Sheet 8. CLOCK GENERATOR
Sheet 9 - 11. DOTHAN
Sheet 12. THERMAL SENSOR / FAN CONTROL
Sheet 13 - 17. RC410MD
Sheet18. DDR II SODIMM
CPU :Intel Dothan -2M Sheet19. DDR TERMINATION
Sheet20 - 23. SB450
Chip Set :RC410MD & SB450 Sheet24. SB450 STRAPS
Sheet25. FWH
Remarks : Mobility Platform Sheet26. LCD C
Sheet27. CRT AND TV CONN
Sheet28-29. CARDBUS
Sheet30. EXPRESS CARD
Sheet31. MINIPCI
Sheet32-34. AUDIO
Model Name : HABANA-C Sheet35. HDD AND ODD
Sheet36. MICOM
PBA Name : MAIN Sheet37. S I/O
Sheet38-39. LAN
PCB Code : BA41-00615A Sheet40. LAN AND MDC CONN
Sheet41. BOARD CONN
Dev. Step : PRR Sheet42. CHARGE
Sheet43. P3.3V _AUX AND P5V_AUX
Revision : 1.0 Sheet44. P1.2V AND VCCP B
Sheet45. DDR2 POWER
T.R. Date : 2005.12.26 Sheet46. CPU VRM
Sheet47. SWITCH POWER
Sheet48. P1.8V_ALW
Sheet49. POWER STRAPS
Sheet50. 1394 BOARD
DRAW CHECK APPROVAL Sheet51. USB BOARD
Sheet52. TOUCH PAD BOARD
Sheet53-55. TP
DS.JIANG DJ.XU KEVINLEE
A
SAMSUNG
Owner : SESC R & D Signature : ELECTRONICS
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THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
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DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
FAN CPU
Mobile Processor VRM
PG 12
IMVP-5
D Dothan - 2M D
CPU Charging
Thermal (533MHz) PG 46
Circuit
LCD Sensor
30P PG 12 L2 Cache : 2 MB PG 42
PG 9,10,11 478pin
PG 26 DDR II
PSB Thermistor
LVDS 667 MT/S PG 16 DDR II Switche PWR
VRM
PG 47
DDR II PG 18 PG 45
CRT/TV
SODIMM 0
PG 27 CRT GMCH-M Single channel DDR II 667/533
DDR II PG 18
Internal Graphics RC410MD SODIMM 1
PG 27 TV
707 FCBGA
SVHS / HDTV ANT
PG 30
PG 13 ~ 17 SD/xD/MS
PG 30
Direct Media Interface
Wireless LAN CARDBUS CardBus
C x4/x2, 1.5V R5C841 PG 30 C
Clocking Mini PCI CONN. R5532V002 EEPROM
PG 31
CK-410M PG 28 ~ 29 1394
64 PIN 33MHz, 3.3V PCI CARDBUS Module 4 pin PG 29
PG 8
USB 0,1,2,3
PG 41 USB 0,1,2,3 ANT
PG 38
AUDIO SB450
Audio 564 BGA PCIE x1 Lane 2 26P
AMP AZALIA AZALIA Primary USB 4 Express Card
PG 30
Codec PG 36
AD1986B 12P
PG 33 PG 32
AZALIA
AZALIA Secondary
RJ11 MDC PG 20 ~ 23 PCI BCM
5751(4401) RJ45
HP & SPDIF. PG 40 Modem
B PG 38~39 B
PG 34 MIC-IN PG 40 PG 40
FWH
2P 2P
SST49LF008A
PG 25
HDD SATA
PG 35
S-ATA
PG 52
SPKR R
Touch
Pri. IDE master PATA 3.3V LPC, 33MHz
MICOM PAD
PG 35
HDD Hitachi H8S
U-ATA 100
Pri. IDE slave
HD64F2169/2160
SPKR L KBD
PG 36 PG 41
A CD-ROM A
PG 35
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Power Diagram
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
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DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
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D KBC3_SUSPWRON KBC3_PWRON KBC3_VRON VCCP3_PWRGD D
AC Adapter VCC_CORE
P1.05V YONAH
NB
P12V_ALWS (VCCP) SB
P1.5V YONAH
VDC P5V_ALWS
P3.3V_ALWS P1.8V_AUX P1.8V
Battery DC
C P0.9V C
MICOM_P3V
P1.8V_ALW
P5V_AUX P5V
KBC3_LANPWRON
P3.3V_LAN P3.3V
P3.3V_AUX P2.5V_LAN
B B
P1.2V_LAN
Rail
State
+V*Always +V*AUX +V SUSPWR PWRON VRON
P1.2V VCC_NB
P1.2V
Full On ON ON ON H H H
S3 ON ON OFF H L L
S4 ON ON OFF H L L
S5 ON OFF OFF L L L
S5 / S4 S3 S0
A A
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PROPRIETARY INFORMATION THAT IS
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DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
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POWER SEQUENCE
VDC
D D
ADT3_SEL
T1=
MICOM_P3V
T2=
KBC3_RST* T3=
P1.8V_ALW
T4=
P5V_ALWS
T5=
PRTC_BAT
T6=
KBC3_PWRSW*
KBC3_LANPWRON T7=112ms
P3.3V_LAN T8=444us
KBC3_SUSPWRON T9=504us
C P5V_AUX/P3.3V_AUX/P1.8V_AUX C
T10=32us
KBC3_RSMRST* T11=380uS
MEM1_VREF
T12=776us
KBC3_PWRBTN*
T13=120.8ms
CHP3_SLPS5*
T14=130ms
CHP3_SLPS3*
T15=130ms
KBC3_PWRON
T16=174ms
P5V/P1.8V/P1.5V/P0.9V
T17=158.4us
KBC3_VRON
VCCP T18=21.4ms
P1.2V/VCC_NB T19=1.5ms
B B
VCCP3_PWRGD T20=1.86ms
VCC_CORE T21=2.34ms
T22=3.88ms
VRM3_CPU_PWRGD
T23=5.02ms
KBC3_CLKPWRGD*
T24=15.12ms
KBC3_NBPWRGD
T25=25.04ms
KBC3_SBPWRGD
T26=136ms
CPU1_PWRGDCPU
T27=184ms
CHP3_ALINK_RST*
T28=187.2ms
PCI3_RST*
T29=188ms
CPU1_CPURST*
A T29=188ms A
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PROPRIETARY INFORMATION THAT IS
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DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG. POWER RAILS ANALYSIS
D ADAPTER D
220V BATTERY
MAX1909ETI+T
P12V_ALWS P1.5V
MMBT3904 SS338A
C C
P0.9V
19V
P5V_ALWS
MAX8550ETI+T
P1.8V_AUX P1.8V
FDS6680A
P3.3V_LAN P3.3V
MAX1999EEI+T FDS6680A
P3.3V_AUX
P5V VCC_CORE
SI4435DY LTC3735
P5V_AUX
VCCP
B ISL6227CAZ-T B
P1.2V
VCC_NB
P3V_ALWS
MICOM_P3V
MIC5219B
P1.8V_ALW
A A
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PROPRIETARY INFORMATION THAT IS
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D CLK0_HCLK0 D
CLK0_HCLK0* DOTHAN
CLK0_HCLK1
CLK0_HCLK1*
CLK1_PCIEICH
RC410MD
CLK1_PCIEICH*
CLK3_NB14M
CLK3_33M_MIN
MINIPCI
CLK3_PCLKLAN
CLK1_PCIERCLK BCM5751
CLK3_PCLKCB
C CLK1_PCIERCLK* R5C843 C
CLK3_PCLKSIO_DS
RS450 CLK3_PCLKSIO LPC
CLK3_USB48
CLK3_PCLKFWH
FWH
CLK3_ICH14 CLK3_PCLKMICOM
MICOM 10MHz
CLOCK GENERATOR 25MHz
CLK1_PCIELOM BCM5751
25MHz
CLK1_PCIELOM* (BCM4401)
CLK1_EXPCARD
B B
CLK1_EXPCARD* EXP CARD
EXP3_CLKREQ*
CLK3_FM48 R5C843 24.576MHz
CLK3_SIO14 LPC47N
14.318 MHz
A A
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PROPRIETARY INFORMATION THAT IS
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SCHEMATIC ANNOTATIONS AND BOARD INFORMATION
D D
PCI Devices Crystal / Oscillator
Devices IDSEL# REQ/GNT# Interrupts TYPE FREQUENCY DEVICE USAGE
Cardbus AD24 0 E,F,G
LAN AD21 1 C Crystal 32.768KHz SB450 Real Time Clock
AD23 2 Crystal 10MHz MICOM HD64F2169/2160
MINIPCI A,B Crystal 14.318MHz CLOCK-Generator CK-410M
USB AD30(internal) - -
- Crystal 24.576MHz Cardbus Controller 1394
- Crystal 25MHz LAN LOM
Hub to PCI AD31(internal) - -
LPC bridge/IDE/AC97/SMBUS AD31(internal) -
- --
Internal MAC AD31(internal) - -
AC Link - - -
Voltage Rails
VCC_CORE CPU
VCCP CPU RC410MD SB450
VCC_NB RC410MD
P1.2V RC410MD VCC_NB
C CPU Core Voltage Table C
P1.5V CPU EXPCARD
P1.8V RC410MD SB450 R5C843 VID(5:0) Voltage VID(5:0) Voltage
P0.9V DDR2
P5V FAN THERMAL CRT SB450 R5C483 MINIPCI AD1986B HDD ODD MICOM USB TOUCH-PAD VCC_CORE 0 0 0 0 0 0 1.708 V 1 0 0 0 0 0 1.196 V
P3.3V SYSTEM POWER 0 0 0 0 0 1 1.692 V 1 0 0 0 0 1 1.180 V
P2.5V_LAN BCM5751 0 0 0 0 1 0 1.676 V 1 0 0 0 1 0 1.164 V
P1.2V_LAN BCM5751 0 0 0 0 1 1 1.660 V 1 0 0 0 1 1 1.148 V
0 0 0 1 0 0 1.644 V 1 0 0 1 0 0 1.132 V
P1.8V_AUX DDR2 P1.8V RC410MD 0 0 0 1 0 1 1.628 V 1 0 0 1 0 1 1.116 V
P5V_AUX THERMAL LCD P1.2V P5V 0 0 0 1 1 0 1.612 V 1 0 0 1 1 0 1.100 V
P3.3V_LAN LCD BCM5751 P3.3V 0 0
- 0 1 1 1 1.596 V 1 -
0 0 1 1 1 1.084 V
P3.3V_AUX MDC MICOM MINIPCI EXP-CARD SB450 THERMAL 0 0 1 0 0 0 1.580 V 1 0 1 0 0 0 1.068 V
P12V_ALWS VCC_NB P1.5V P3.3V P1,8V 0 0 1 0 0 1 1.564 V 1 0 1 0 0 1 1.052 V
0 0 1 0 1 0 1.548 V 1 0 1 0 1 0 1.036 V
P5V_ALWS P3.3V DDR2-PWR 0 0 1 0 1 1 1.532 V 1 0 1 0 1 1 1.020 V
P3.3V_ALWS MICOM_P3V 0 0 1 1 0 0 1.516 V 1 0 1 1 0 0 1.004 V
MICOM_P3V THERMAL SB450 MICOM LED P1.8V_ALWS 0 0 1 1 0 1 1.500 V 1 0 1 1 0 1 0.988 V Lowest Freq.
P1.8V_ALW SB450 0 0 1 1 1 0 1.484 V 1 0 1 1 1 0 0.972 V
0 0 1 1 1 1 1.468 V 1 0 1 1 1 1 0.956 V
VDC Primary DC system power supply (7 to 21V) 0 1 0 0 0 0 1.452 V 1 1 0 0 0 0 0.940 V
0 1 0 0 0 1 1.436 V 1 1 0 0 0 1 0.924 V
2 0 1 0 0 1 0 1.420 V 1 1 0 0 1 0 0.908 V
0 1 0 0 1 1 1.404 V 1 1 0 0 1 1 0.892 V
I C / SMB Address 0 1 0 1 0 0 1.388 V 1 1 0 1 0 0 0.876 V
Devices Address Hex Bus 0 1 0 1 0 1 1.372 V 1 1 0 1 0 1 0.860 V
0 1 0 1 1 0 1.356 V 1 1 0 1 1 0 0.844 V
0 1 0 1 1 1 1.340 V 1 1 0 1 1 1 0.828 V
SB450 Master - SMBUS Master
B 0 1 1 0 0 0 1.324 V 1 1 1 0 0 0 0.812 V B
EMC6N300(CPU Thermal Sensor) 1001 110X 9Ch Thermal Sensor 0 1 1 0 0 1 1.308 V 1 1 1 0 0 1 0.796 V
SODIMM0 1010 0000 A0h -
SODIMM1 1010 001X A2h - 0 1 1 0 1 0 1.292 V 1 1 1 0 1 0 0.780 V
0 1 1 0 1 1 1.276 V 1 1 1 0 1 1 0.764 V
CK-408 (Clock Generator) 1101 001x D2h Clock, Unused Clock Output Disable
0 1 1 1 0 0 1.260 V 1 1 1 1 0 0 0.748 V
0 1 1 1 0 1 1.244 V 1 1 1 1 0 1 0.732 V
0 1 1 1 1 0 1.228 V 1 1 1 1 1 0 0.716 V
0 1 1 1 1 1 1.212 V 1 1 1 1 1 1 0.700 V
HFM Voltage
USB PORT Assign 770:1.26V->1.372V
730,740,750,760:1.26->1.356V
PORT NUMBER ASSIGNED TO
0 SYSTEM PORT A
1,2 SYSTEM PORT B
3 SYSTEM PORT C
4 EXPRESS CARD
System Power States
CHP3_SLPS1* S1, Powered-On-Suspend(POS) : In this state, all clocks(except the 32.768KHz clock) are stopped.
The system context is maintained in system DRAM. Power is maintained to PCI, the CPU, memory controller, memory, and all other criticial subsystems.
A Note that this state does not preclude power being removed from non-essential devices, such as disk drives. During this state, CPU can be selected A
for either Deep Sleep or Deeper Sleep.
In Deeper Sleep, CPU voltage reduced in this state to reduce the leakage power.
CHP3_SLPS3* S3, Suspend-To-RAM(STR) : The system context is maintained in system DRAM, but power is shut off to non-critical circuits.
Memory is retained, and refreshes continue. All clocks stop except RTC clock. SAMSUNG
CHP3_SLP4S* S4, Suspend-To-Disk(STD) : The Context of the system is maintained on the disk. All power is then shut off to the system except for the logic required to resume. ELECTRONICS
Externally appears same as S5, but may have different wake events.
CHP3_SLPS5* S5, Soft Off(SOFF) : System context is not maintained. All power is shut off except for the logic required to restart. A full boot is required when waking.
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FSA FSB FSC
HOST CLK P3.3V
D CPU BSEL0 BSEL1 BSEL2 Pt decoupling CAPS close to ICS951411 power pin
D
MMZ1608S121AT
0 0 0 266 MHz B24
0 0 1 333 MHz
100nF
100nF
100nF
100nF
100nF
100nF
100nF
0 1 0 200 MHz
0 1 1 400 MHz C207 P3.3V
10000nF
1 0 0 133 MHz
C245
C187
C211
C209
C208
C213
C212
6.3V
1 0 1 100 MHz
B20
MMZ1608S121AT
1 1 0 166 MHz
1 1 1 RSVD
100nF
P3.3V
FSB STUFF NO STUFF U15
C186
ICS951411BG 10000nF R162
400MHz R119,R141,R113 R121,R140,R112 45 39 4.7K
C210
VDDCPU VDDA 6.3V
35 38
VDD_SRC VSSA
32
21
VDD_SRC1
47