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CONFIDENTIAL
10 Schematic Diagrams
10-1 CPU Block & Analog Signal Input Processing Part Schematic Diagram
20 26 32 38 44

+3.3V_A

TO DPTV MCAD(0:7) MCAD(0:7)
to MUX PARALLEL COMM
C602
100nF




DGCPU DGCPU
MCA(0:19) MCA(0:19)
3230Y_OUT(0:7) AD(0:7) +3.3V_A




MCAD(5)
MCAD(0)
MCAD(6)

MCAD(7)
MCA(0)
MCA(1)
MCA(2)


MCA(10)
MCA(3)


MCA(4)

MCA(5)
MCA(9)
MCA(6)
MCA(8)




MCA(12)

MCA(15)

MCA(16)


DGROM

MCA(18)

MCA(17)
MCA(11)
3230Y_OUT(7)

3230Y_OUT(6)

3230Y_OUT(5)

3230Y_OUT(4)

3230Y_OUT(3)

3230Y_OUT(2)

3230Y_OUT(1)

3230Y_OUT(0)
3230C_OUT(0:7) DG32 G02 DGROM C604
C066
C620




3230C_OUT(7)

3230C_OUT(6)

3230C_OUT(5)

3230C_OUT(4)

3230C_OUT(3)

3230C_OUT(2)

3230C_OUT(1)

3230C_OUT(0)
100uF 47uF
100nF