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PIC12CE5XX
8-Pin, 8-Bit CMOS Microcontroller with
EEPROM Data Memory
Devices: Pin Diagram:
PIC12CE518 and PIC12CE519 are 8-bit microcontrol- PDIP, SOIC, Windowed CERDIP
lers packaged in 8-lead packages. They are based on
the Enhanced PIC16C5X family. VDD 1 8 VSS
PIC12CE519
PIC12CE518
GP5/OSC1/CLKIN GP0
High-Performance RISC CPU: 2 7
GP4/OSC2 3 6 GP1
· Only 33 single word instructions to learn
GP3/MCLR/VPP 4 5 GP2/T0CKI
· All instructions are single cycle (1 µs) except for
program branches which are two-cycle
· Operating speed: DC - 4 MHz clock input
DC - 1 µs instruction cycle Special Microcontroller Features:
Memory · In-Circuit Serial Programming (ICSPTM) of pro-
gram memory (via two pins)
Device EPROM RAM EEPROM · Internal 4 MHz RC oscillator with programmable
Program Data Data calibration
· Power-on Reset (POR)
PIC12CE518 512 x 12 25 x 8 16 x 8
· Device Reset Timer (DRT)
PIC12CE519 1024 x 12 41 x 8 16 x 8 · Watchdog Timer (WDT) with its own on-chip RC
· 12-bit wide instructions oscillator for reliable operation
· 8-bit wide data path · Programmable code-protection
· Special function hardware registers · Power saving SLEEP mode
· Two-level deep hardware stack · Wake-up from SLEEP on pin change
· Direct, indirect and relative addressing modes for · Internal weak pull-ups on I/O pins
data and instructions · Internal pull-up on MCLR pin
· Selectable oscillator options:
Peripheral Features:
- INTRC: Internal 4 MHz RC oscillator
· 8-bit real-time clock/counter (TMR0) with 8-bit - EXTRC: External low-cost RC oscillator
programmable prescaler - XT: Standard crystal/resonator
· 1,000,000 erase/write cycle EEPROM data - LP: Power saving, low frequency crystal
memory
· EEPROM data retention > 40 years CMOS Technology:
· Low-power, high-speed CMOS EPROM/
EEPROM technology
· Fully static design
· Wide temperature range:
- Commercial: 0°C to +70°C
- Industrial: -40°C to +85°C
- Extended: -40°C to +125°C
· Wide operating voltage range:
-Commercial: 3.0V to 5.5V
-Industrial: 3.0V to 5.5V
-Extended: 4.5V to 5.5V
· Low power consumption
- < 2 mA typical @ 5V, 4 MHz
- 15 µA typical @ 3V, 32 kHz
- < 1 µA typical standby current
© 1997 Microchip Technology Inc. Preliminary DS40172A-page 1
PIC12CE5XX
TABLE OF CONTENTS
1.0 General Description..................................................................................................................................................................... 3
2.0 PIC12CE5XX Device Varieties.................................................................................................................................................... 5
3.0 Architectural Overview ................................................................................................................................................................ 7
4.0 Memory Organization ................................................................................................................................................................ 11
5.0 PIC12CE518I/O Port ................................................................................................................................................................. 19
6.0 EEPROM Peripheral Operation................................................................................................................................................. 21
7.0 Timer0 Module and TMR0 Register .......................................................................................................................................... 25
8.0 Special Features of the CPU..................................................................................................................................................... 29
9.0 Instruction Set Summary ........................................................................................................................................................... 41
10.0 Development Support................................................................................................................................................................ 53
11.0 Electrical Characteristics - PIC12CE5XX .................................................................................................................................. 57
12.0 DC and AC Characteristics - PIC12CE5XX .............................................................................................................................. 69
13.0 Packaging Information............................................................................................................................................................... 73
14.0 Appendix A ................................................................................................................................................................................ 77
Index .................................................................................................................................................................................................... 83
PIC12CE5XX Product Identification System........................................................................................................................................ 87
To Our Valued Customers
We constantly strive to improve the quality of all our products and documentation. We have spent an exceptional
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DS40172A-page 2 Preliminary © 1997 Microchip Technology Inc.
PIC12CE5XX
1.0 GENERAL DESCRIPTION 1.1 Applications
The 8-pin PIC12CE5XX from Microchip Technology is The PIC12CE5XX series fits perfectly in applications
a family of low-cost, high performance, 8-bit, fully static, ranging from sensory systems, gas detectors and
EPROM/EEPROM-based CMOS microcontrollers. It security systems to low-power remote transmitters/
employs a RISC architecture with only 33 single word/ receivers. The EPROM programming technology
single cycle instructions. All instructions are single makes customizing application programs (transmitter
cycle (1 µs) except for program branches which take codes, appliance settings, receiver frequencies, etc.)
two cycles. The PIC12CE5XX delivers performance an extremely fast and convenient. While the EEPROM
order of magnitude higher than its competitors in the data memory technology allows for the changing of cal-
same price category. The 12-bit wide instructions are ibrations factors and security codes, the small footprint
highly symmetrical resulting in 2:1 code compression 8-pin packages, for through hole or surface mounting,
over other 8-bit microcontrollers in its class. The easy make this microcontroller series perfect for applications
to use and easy to remember instruction set reduces with space limitations. Low-cost, low-power, high per-
development time significantly. formance, ease of use and I/O flexibility make the
The PIC12CE5XX products are equipped with special PIC12CE5XX series very versatile even in areas where
features that reduce system cost and power require- no microcontroller use has been considered before
ments. The Power-On Reset (POR) and Device Reset (e.g., timer functions, replacement of "glue" logic and
Timer (DRT) eliminate the need for external reset cir- PLD's in larger systems, coprocessor applications).
cuitry. There are four oscillator configurations to choose
from, including INTRC internal oscillator mode and the
power-saving LP (Low Power) oscillator. Power saving
SLEEP mode, Watchdog Timer and code protection
features improve system cost, power and reliability.
The PIC12CE5XX are available in the cost-effective
One-Time-Programmable (OTP) versions which are
suitable for production in any volume. The customer
can take full advantage of Microchip's price leadership
in OTP microcontrollers while benefiting from the OTP's
flexibility.
The PIC12CE5XX products are supported by a full-fea-
tured macro assembler, a software simulator, an in-cir-
cuit emulator, a `C' compiler, fuzzy logic support tools,
a low-cost development programmer, and a full fea-
tured programmer. All the tools are supported on IBM®
PC and compatible machines.
© 1997 Microchip Technology Inc. Preliminary DS40172A-page 3
PIC12CE5XX
TABLE 1-1: PIC12CXXX FAMILY OF DEVICES
PIC12C508(A) PIC12C509(A) PIC12CE518 PIC12CE519 PIC12C671 PIC12C672
Maximum Frequency 4 4 4 4 10 10
Clock
of Operation (MHz)
EPROM Program 512 x 12 1024 x 12 512 x 12 1024 x 12 1024 x 14 2048 x 14
Memory
Memory
RAM Data Memory 25 41 25 41 128 128
(bytes)
EEPROM Data Mem- 16 16
ory (bytes)
Peripherals Timer Module(s) TMR0 TMR0 TMR0 TMR0 TMR0 TMR0
A/D Converter (8-bit) -- -- -- -- 4 4
Channels
Wake-up from Yes Yes Yes Yes Yes Yes
SLEEP on
pin change
Interrupt Sources -- -- 4 4
Features I/O Pins 5 5 5 5 5 5
Input Pins 1 1 1 1 1 1
Internal Pull-ups Yes Yes Yes Yes Yes Yes
In-Circuit Serial Pro- Yes Yes Yes Yes Yes Yes
gramming
Number of Instruc- 33 33 33 33 35 35
tions
Packages 8-pin DIP, 8-pin DIP, 8-pin DIP, 8-pin DIP, 8-pin DIP, 8-pin DIP,
JW, SOIC JW, SOIC JW, SOIC JW, SOIC JW, SOIC JW, SOIC
All PIC12CE5XX devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability.
All PIC12CE5XX devices use serial programming with data pin GP0 and clock pin GP1.
DS40172A-page 4 Preliminary © 1997 Microchip Technology Inc.
PIC12CE5XX
2.0 PIC12CE5XX DEVICE 2.3 Quick-Turnaround-Production (QTP)
VARIETIES Devices
A variety of packaging options are available. Microchip offers a QTP Programming Service for
Depending on application and production factory production orders. This service is made
requirements, the proper device option can be available for users who choose not to program a
selected using the information in this section. When medium to high quantity of units and whose code
placing orders, please use the PIC12CE5XX Product patterns have stabilized. The devices are identical to
Identification System at the back of this data sheet to the OTP devices but with all EPROM locations and fuse
specify the correct part number. options already programmed by the factory. Certain
code and prototype verification procedures do apply
2.1 UV Erasable Devices before production shipments are available. Please con-
tact your local Microchip Technology sales office for
The UV erasable version, offered in windowed cerdip
more details.
package, is optimal for prototype development and
pilot programs. 2.4 Serialized Quick-Turnaround
The UV erasable version can be erased and Production (SQTPSM) Devices
reprogrammed to any of the configuration modes.
Microchip offers a unique programming service where
Note: Please note that erasing the device will a few user-defined locations in each device are
also erase the pre-programmed internal programmed with different serial numbers. The serial
calibration value for the internal oscillator. numbers may be random, pseudo-random or
The calibration value must be saved prior sequential.
to erasing the part.
Serial programming allows each device to have a
Microchip's PICSTART® PLUS and PRO MATE® pro- unique number which can serve as an entry-code,
grammers all support programming of the password or ID number.
PIC12CE5XX. Third party programmers also are avail-
able; refer to the Microchip Third Party Guide for a list
of sources.
2.2 One-Time-Programmable (OTP)
Devices
The availability of OTP devices is especially useful for
customers who need the flexibility for frequent code
updates or small volume applications.
The OTP devices, packaged in plastic packages permit
the user to program them once. In addition to the
program memory, the configuration bits must also be
programmed.
© 1997 Microchip Technology Inc. Preliminary DS40172A-page 5
PIC12CE5XX
NOTES:
DS40172A-page 6 Preliminary © 1997 Microchip Technology Inc.
PIC12CE5XX
3.0 ARCHITECTURAL OVERVIEW The PIC12CE5XX device contains an 8-bit ALU and
working register. The ALU is a general purpose
The high performance of the PIC12CE5XX family can arithmetic unit. It performs arithmetic and Boolean
be attributed to a number of architectural features functions between data in the working register and any
commonly found in RISC microprocessors. To begin register file.
with, the PIC12CE5XX uses a Harvard architecture in
which program and data are accessed on separate The ALU is 8-bits wide and capable of addition,
buses. This improves bandwidth over traditional von subtraction, shift and logical operations. Unless
Neumann architecture where program and data are otherwise mentioned, arithmetic operations are two's
fetched on the same bus. Separating program and complement in nature. In two-operand instructions,
data memory further allows instructions to be sized typically one operand is the W (working) register. The
differently than the 8-bit wide data word. Instruction other operand is either a file register or an immediate
opcodes are 12-bits wide making it possible to have all constant. In single operand instructions, the operand
single word instructions. A 12-bit wide program is either the W register or a file register.
memory access bus fetches a 12-bit instruction in a The W register is an 8-bit working register used for
single cycle. A two-stage pipeline overlaps fetch and ALU operations. It is not an addressable register.
execution of instructions. Consequently, all instructions
Depending on the instruction executed, the ALU may
(33) execute in a single cycle (1µs @ 4MHz) except for
affect the values of the Carry (C), Digit Carry (DC),
program branches.
and Zero (Z) bits in the STATUS register. The C and
The PIC12CE518 addresses 512 x 12 of program DC bits operate as a borrow and digit borrow out bit,
memory, the PIC12CE519 addresses 1K x 12 of respectively, in subtraction. See the SUBWF and ADDWF
program memory. All program memory is internal. instructions for examples.
The PIC12CE5XX can directly or indirectly address its A simplified block diagram is shown in Figure 3-1, with
register files and data memory. All special function the corresponding device pins described in Table 3-1.
registers including the program counter are mapped in
the data memory. The PIC12CE5XX has a highly
orthogonal (symmetrical) instruction set that makes it
possible to carry out any operation on any register
using any addressing mode. This symmetrical nature
and lack of `special optimal situations' make
programming with the PIC12CE5XX simple yet
efficient. In addition, the learning curve is reduced
significantly.
The PIC12CE5XX contains a 16 X 8 EEPROM
memory array for storing non-volatile information such
as calibration data or security codes. This memory
has an endurance of 1,000,000 erase/write cycles and
a retention of 40+ years.
© 1997 Microchip Technology Inc. Preliminary DS40172A-page 7
PIC12CE5XX
FIGURE 3-1: PIC12CE5XX BLOCK DIAGRAM
12 8 GPIO
Data Bus
EPROM Program Counter
512 x 12 or GP0
1024 x 12 GP1
RAM GP2/T0CKI
Program 25 x 8 or
Memory STACK1 GP3/MCLR/VPP
41 x 8 GP4/OSC2
STACK2 File
Registers GP5/OSC1/CLKIN
Program 12
RAM Addr 9
SDA
Bus
SCL
Addr MUX
Instruction reg
Direct Addr 5 Indirect
5-7 Addr
FSR reg 16 X 8
EEPROM
STATUS reg Data
8 Memory
3 MUX
Device Reset
Timer
Instruction
Decode & ALU
Control Power-on
Reset
8
OSC1/CLKIN Timing Watchdog
Generation Timer W reg
OSC2
Internal RC
OSC Timer0
MCLR
VDD, VSS
DS40172A-page 8 Preliminary © 1997 Microchip Technology Inc.
PIC12CE5XX
TABLE 3-1: PIC12CE5XX PINOUT DESCRIPTION
DIP SOIC I/O/P Buffer
Name Description
Pin # Pin # Type Type
GP0 7 7 I/O TTL/ST Bi-directional I/O port/ serial programming data. Can
be software programmed for internal weak pull-up and
wake-up from SLEEP on pin change. This buffer is a
Schmitt Trigger input when used in serial programming
mode.
GP1 6 6 I/O TTL/ST Bi-directional I/O port/ serial programming clock. Can
be software programmed for internal weak pull-up and
wake-up from SLEEP on pin change. This buffer is a
Schmitt Trigger input when used in serial programming
mode.
GP2/T0CKI 5 5 I/O ST Bi-directional I/O port. Can be configured as T0CKI.
GP3/MCLR/VPP 4 4 I TTL Input port/master clear (reset) input/programming volt-
age input. When configured as MCLR, this pin is an
active low reset to the device. Voltage on MCLR/VPP
must not exceed VDD during normal device operation.
Can be software programmed for internal weak pull-up
and wake-up from SLEEP on pin change. Weak pull-
up always on if configured as MCLR
GP4/OSC2 3 3 I/O TTL Bi-directional I/O port/oscillator crystal output. Con-
nections to crystal or resonator in crystal oscillator
mode (XT and LP modes only, GPIO in other modes).
GP5/OSC1/CLKIN 2 2 I/O TTL/ST Bidirectional IO port/oscillator crystal input/external
clock source input (GPIO in Internal RC mode only,
OSC1 in all other oscillator modes). TTL input when
GPIO, ST input in external RC oscillator mode.
VDD 1 1 P -- Positive supply for logic and I/O pins
VSS 8 8 P -- Ground reference for logic and I/O pins
Legend: I = input, O = output, I/O = input/output, P = power, -- = not used, TTL = TTL input,
ST = Schmitt Trigger input
© 1997 Microchip Technology Inc. Preliminary DS40172A-page 9
PIC12CE5XX
3.1 Clocking Scheme/Instruction Cycle 3.2 Instruction Flow/Pipelining
The clock input (OSC1/CLKIN pin) is internally divided An Instruction Cycle consists of four Q cycles (Q1, Q2,
by four to generate four non-overlapping quadrature Q3 and Q4). The instruction fetch and execute are
clocks namely Q1, Q2, Q3 and Q4. Internally, the pipelined such that fetch takes one instruction cycle
program counter is incremented every Q1, and the while decode and execute takes another instruction
instruction is fetched from program memory and cycle. However, due to the pipelining, each instruction
latched into instruction register in Q4. It is decoded effectively executes in one cycle. If an instruction
and executed during the following Q1 through Q4. The causes the program counter to change (e.g., GOTO)
clocks and instruction execution flow is shown in then two cycles are required to complete the
Figure 3-2 and Example 3-1. instruction (Example 3-1).
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is
latched into the Instruction Register (IR) in cycle Q1.
This instruction is then decoded and executed during
the Q2, Q3, and Q4 cycles. Data memory is read
during Q2 (operand read) and written during Q4
(destination write).
FIGURE 3-2: CLOCK/INSTRUCTION CYCLE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Q1
Q2 Internal
phase
Q3 clock
Q4
PC PC PC+1 PC+2
Fetch INST (PC)
Execute INST (PC-1) Fetch INST (PC+1)
Execute INST (PC) Fetch INST (PC+2)
Execute INST (PC+1)
EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW
1. MOVLW 03H Fetch 1 Execute 1
2. MOVWF GPIO Fetch 2 Execute 2
3. CALL SUB_1 Fetch 3 Execute 3
4. BSF GPIO, BIT1 Fetch 4 Flush
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch
instruction is "flushed" from the pipeline while the new instruction is being fetched and then executed.
DS40172A-page 10 Preliminary © 1997 Microchip Technology Inc.
PIC12CE5XX
4.0 MEMORY ORGANIZATION FIGURE 4-1: PROGRAM MEMORY MAP
AND STACK FOR THE
PIC12CE5XX memory is organized into program mem-
ory and data memory. For devices with more than 512 PIC12CE5XX
bytes of program memory, a paging scheme is used. PC<11:0>
Program memory pages are accessed using one STA- CALL, RETLW 12
TUS register bit. For the PIC12CE519 with a data
memory register file of more than 32 registers, a bank- Stack Level 1
ing scheme is used. Data memory banks are accessed Stack Level 2
using the File Select Register (FSR).
4.1 Program Memory Organization Reset Vector (note 1) 0000h
The PIC12CE5XX devices have a 12-bit Program
Counter (PC) capable of addressing a 2K x 12 On-chip Program
program memory space. Memory
User Memory
Only the first 512 x 12 (0000h-01FFh) for the
Space
PIC12CE518 and 1K x 12 (0000h-03FFh) for the
512 Word (PIC12CE518) 01FFh
PIC12CE519 are physically implemented. Refer to
0200h
Figure 4-1. Accessing a location above these
boundaries will cause a wrap-around within the first
On-chip Program
512 x 12 space (PIC12CE518) or 1K x 12 space Memory
(PIC12CE519). The effective reset vector is at 000h,
(see Figure 4-1). Location 01FFh (PIC12CE518) or
location 03FFh (PIC12CE519), the hardwired reset 1024 Word (PIC12CE519) 03FFh
vector location, contains the internal clock oscillator 0400h
calibration value. This value is set at Microchip and
should never be overwritten. Upon reset, the
MOVLW XX is executed, the PC wraps to location
0000h, thus making 0000h the effective reset vector.
7FFh
Note 1: Address 0000h becomes the
effective reset vector. Location
01FFh (PIC12CE518) or location
03FFh (PIC12CE519) contains the
MOVLW XX INTRC oscillator
calibration value.
© 1997 Microchip Technology Inc. Preliminary DS40172A-page 11
PIC12CE5XX
4.2 Data Memory Organization FIGURE 4-2: PIC12CE518 REGISTER FILE
MAP
Data memory is composed of registers, or bytes of
RAM. Therefore, data memory for a device is specified File Address
by its register file. The register file is divided into two
00h INDF(1)
functional groups: special function registers and
general purpose registers. 01h TMR0
The special function registers include the TMR0 02h PCL
register, the Program Counter (PC), the Status 03h STATUS
Register, the I/O registers (ports), and the File Select
04h FSR
Register (FSR). In addition, special purpose registers
are used to control the I/O port configuration and 05h OSCCAL
prescaler options. 06h GPIO
The general purpose registers are used for data and 07h
control information under command of the instructions.
For the PIC12CE518, the register file is composed of 7
special function registers and 25 general purpose General
registers (Figure 4-2). Purpose
Registers
For the PIC12CE519, the register file is composed of 7
special function registers, 25 general purpose
registers, and 16 general purpose registers that may
be addressed using a banking scheme (Figure 4-3). 1Fh
4.2.1 GENERAL PURPOSE REGISTER FILE
Note 1: Not a physical register. See Indirect
Data Addressing, Section 4.8.
The general purpose register file is accessed either
directly or indirectly through the file select register
FSR (Section 4.8).
FIGURE 4-3: PIC12CE519 REGISTER FILE MAP
FSR<6:5> 00 01
File Address
00h INDF(1) 20h
01h TMR0
02h PCL
03h STATUS Addresses map
back to
04h FSR addresses
05h OSCCAL in Bank 0.
06h GPIO
07h
General
Purpose
Registers
0Fh 2Fh
10h 30h
General General
Purpose Purpose
Registers Registers
1Fh 3Fh
Bank 0 Bank 1
Note 1: Not a physical register. See Indirect
Data Addressing, Section 4.8.
DS40172A-page 12 Preliminary © 1997 Microchip Technology Inc.
PIC12CE5XX
4.2.2 SPECIAL FUNCTION REGISTERS The special registers can be classified into two sets.
The special function registers associated with the
The Special Function Registers (SFRs) are registers "core" functions are described in this section. Those
used by the CPU and peripheral functions to control related to the operation of the peripheral features are
the operation of the device (Table 4-1). described in the section for each peripheral feature.
TABLE 4-1: SPECIAL FUNCTION REGISTER (SFR) SUMMARY
Value on Value on Value on
Power-On MCLR and Wake-up on
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset WDT Reset Pin Change
N/A TRIS -- -- I/O control registers --11 1111 --11 1111 --11 1111
Contains control bits to configure Timer0, Timer0/WDT
N/A OPTION prescaler, wake-up on change, and weak pull-ups 1111 1111 1111 1111 1111 1111
Uses contents of FSR to address data memory (not a physical
00h INDF register) xxxx xxxx uuuu uuuu uuuu uuuu
01h TMR0 8-bit real-time clock/counter xxxx xxxx uuuu uuuu uuuu uuuu
02h(1) PCL Low order 8 bits of PC 1111 1111 1111 1111 1111 1111
03h STATUS GPWUF -- PA0 TO PD Z DC C 0001 1xxx 000q quuu 100q quuu
FSR
04h (12CE518) Indirect data memory address pointer 111x xxxx 111u uuuu 111u uuuu
FSR
04h (12CE519) Indirect data memory address pointer 110x xxxx 11uu uuuu 11uu uuuu
OSCCAL
(12CE518/
12CE519)
05h CAL7 CAL6 CAL5 CAL4 CALFST CALSLW -- -- 0111 00-- uuuu uu-- uuuu uu--
06h GPIO SCL SDA GP5 GP4 GP3 GP2 GP1 GP0 11xx xxxx 11uu uuuu 11uu uuuu
Legend: Shaded boxes = unimplemented or unused, -- = unimplemented, read as '0' (if applicable)
x = unknown, u = unchanged, q = see the tables in Section 8.7 for possible values.
Note 1: The upper byte of the Program Counter is not directly accessible. See Section 4.6
for an explanation of how to access these bits.
© 1997 Microchip Technology Inc. Preliminary DS40172A-page 13
PIC12CE5XX
4.2.3 EEPROM DATA MEMORY For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS register
The PIC12CE518 and PIC12CE519 each have 16 as 000u u1uu (where u = unchanged).
bytes of EEPROM data memory. The EEPROM data
memory supports a bi-directional 2-wire bus and data It is recommended, therefore, that only BCF, BSF and
transmission protocol. Refer to Section 6.0 on MOVWF instructions be used to alter the STATUS
EEPROM Peripherals. register because these instructions do not affect the Z,
DC or C bits from the STATUS register. For other
4.3 STATUS Register instructions, which do affect STATUS bits, see
Instruction Set Summary.
This register contains the arithmetic status of the ALU,
the RESET status, and the page preselect bit for
program memories larger than 512 words.
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to
the device logic. Furthermore, the TO and PD bits are
not writable. Therefore, the result of an instruction with
the STATUS register as destination may be different
than intended.
FIGURE 4-4: STATUS REGISTER (ADDRESS:03h)
R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
GPWUF -- PA0 TO PD Z DC C R = Readable bit
bit7 6 5 4 3 2 1 bit0 W = Writable bit
- n = Value at POR reset
bit 7: GPWUF: GPIO reset bit
1 = Reset due to wake-up from SLEEP on pin change
0 = After power up or other reset
bit 6: Unimplemented
bit 5: PA0: Program page preselect bits
1 = Page 1 (200h - 3FFh) - PIC12CE519
0 = Page 0 (000h - 1FFh) - PIC12CE518 and PIC12CE519
Each page is 512 bytes.
Using the PA0 bit as a general purpose read/write bit in devices which do not use it for program
page preselect is not recommended since this may affect upward compatibility with future products.
bit 4: TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3: PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2: Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1: DC: Digit carry/borrow bit (for ADDWF and SUBWF instructions)
ADDWF
1 = A carry from the 4th low order bit of the result occurred
0 = A carry from the 4th low order bit of the result did not occur
SUBWF
1 = A borrow from the 4th low order bit of the result did not occur
0 = A borrow from the 4th low order bit of the result occurred
bit 0: C: Carry/borrow bit (for ADDWF, SUBWF and RRF, RLF instructions)
ADDWF SUBWF RRF or RLF
1 = A carry occurred 1 = A borrow did not occur Load bit with LSB or MSB, respectively
0 = A carry did not occur 0 = A borrow occurred
DS40172A-page 14 Preliminary © 1997 Microchip Technology Inc.
PIC12CE5XX
4.4 OPTION Register
Note: If TRIS bit is set to `0', the wake-up on
The OPTION register is a 8-bit wide, write-only change and pull-up functions are disabled
register which contains various control bits to for that pin; i.e., note that TRIS overrides
configure the Timer0/WDT prescaler and Timer0. OPTION control of GPPU and GPWU.
By executing the OPTION instruction, the contents of Note: If the T0CS bit is set to `1', GP2 is forced to
the W register will be transferred to the OPTION be an input even if TRIS GP2 = `0'.
register. A RESET sets the OPTION<7:0> bits.
FIGURE 4-5: OPTION REGISTER
W-1 W-1 W-1 W-1 W-1 W-1 W-1 W-1
GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 W = Writable bit
bit7 6 5 4 3 2 1 bit0 U = Unimplemented bit
- n = Value at POR reset
Reference Table 4-1 for
other resets.
bit 7: GPWU: Enable wake-up on pin change (GP0, GP1, GP3)
1 = Disabled
0 = Enabled
bit 6: GPPU: Enable weak pull-ups (GP0, GP1, GP3)
1 = Disabled
0 = Enabled
bit 5: T0CS: Timer0 clock source select bit
1 = Transition on T0CKI pin
0 = Transition on internal instruction cycle clock, Fosc/4
bit 4: T0SE: Timer0 source edge select bit
1 = Increment on high to low transition on the T0CKI pin
0 = Increment on low to high transition on the T0CKI pin
bit 3: PSA: Prescaler assignment bit
1 = Prescaler assigned to the WDT
0 = Prescaler assigned to Timer0
bit 2-0: PS2:PS0: Prescaler rate select bits
Bit Value Timer0 Rate WDT Rate
000 1:2 1:1
001 1:4 1:2
010 1:8 1:4
011 1 : 16 1:8
100 1 : 32 1 : 16
101 1 : 64 1 : 32
110 1 : 128 1 : 64
111 1 : 256 1 : 128
© 1997 Microchip Technology Inc. Preliminary DS40172A-page 15
PIC12CE5XX
4.5 OSCCAL Register
The Oscillator Calibration (OSCCAL) register is used to
calibrate the internal 4 MHz oscillator. It contains four
bits for fine calibration and two other bits to either
increase or decrease frequency.
FIGURE 4-6: OSCCAL REGISTER (ADDRESS 8Fh)
R/W-0 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 U-0 U-0
CAL3 CAL2 CAL1 CAL0 CALFST CALSLW -- -- R = Readable bit
bit7 bit0 W = Writable bit
U = Unimplemented bit,
read as `0'
- n = Value at POR reset
bit 7-4: CAL<3:0>: Fine calibration
bit 3: CALFST: Calibration Fast
1 = Increase frequency
0 = No change
bit 2: CALSLW: Calibration Slow
1 = Decrease frequency
0 = No change
bit 1-0: Unimplemented: Read as '0'
Note: If CALFST = 1 and CALSLW = 1, CALFST has precedence.
DS40172A-page 16 Preliminary © 1997 Microchip Technology Inc.
PIC12CE5XX
4.6 Program Counter 4.6.1 EFFECTS OF RESET
As a program instruction is executed, the Program The Program Counter is set upon a RESET, which
Counter (PC) will contain the address of the next means that the PC addresses the last location in the
program instruction to be executed. The PC value is last page i.e., the oscillator calibration instruction. After
increased by one every instruction cycle, unless an executing MOVLW XX, the PC will roll over to location
instruction changes the PC. 00h, and begin executing user code.
For a GOTO instruction, bits 8:0 of the PC are provided The STATUS register page preselect bits are cleared
by the GOTO instruction word. The PC Latch (PCL) is upon a RESET, which means that page 0 is pre-
mapped to PC<7:0>. Bit 5 of the STATUS register selected.
provides page information to bit 9 of the PC (Figure 4- Therefore, upon a RESET, a GOTO instruction will
7). automatically cause the program to jump to page 0
For a CALL instruction, or any instruction where the until the value of the page bits is altered.
PCL is the destination, bits 7:0 of the PC again are
provided by the instruction word. However, PC<8> 4.7 Stack
does not come from the instruction word, but is always
PIC12CE5XX devices have a 12-bit wide hardware
cleared (Figure 4-7).
push/pop stack.
Instructions where the PCL is the destination, or
A CALL instruction will push the current value of stack
Modify PCL instructions, include MOVWF PC, ADDWF
1 into stack 2 and then push the current program
PC, and BSF PC,5.
counter value, incremented by one, into stack level 1. If
Note: Because PC<8> is cleared in the CALL more than two sequential CALL are executed, only
's
instruction, or any Modify PCL instruction, the most recent two return addresses are stored.
all subroutine calls or computed jumps are A RETLW instruction will pop the contents of stack level
limited to the first 256 locations of any pro- 1 into the program counter and then copy stack level 2
gram memory page (512 words long). contents into level 1. If more than two sequential
FIGURE 4-7: LOADING OF PC RETLW's are executed, the stack will be filled with the
address previously stored in level 2. Note that the
BRANCH INSTRUCTIONS -
W register will be loaded with the literal value specified
PIC12CE518/CE519
in the instruction. This is particularly useful for the
GOTO Instruction implementation of data look-up tables within the
program memory.
11 10 9 8 7 0
PC PCL
Instruction Word
PA0
7 0
STATUS
CALL or Modify PCL Instruction
11 10 9 8 7 0
PC PCL
Instruction Word
Reset to `0'
PA0
7 0
STATUS
© 1997 Microchip Technology Inc. Preliminary DS40172A-page 17
PIC12CE5XX
4.8 Indirect Data Addressing; INDF and EXAMPLE 4-2: HOW TO CLEAR RAM
FSR Registers USING INDIRECT
ADDRESSING
The INDF register is not a physical register. movlw 0x10 ;initialize pointer
Addressing INDF actually addresses the register movwf FSR ; to RAM
whose address is contained in the FSR register (FSR NEXT clrf INDF ;clear INDF register
is a pointer). This is indirect addressing. incf FSR,F ;inc pointer
btfsc FSR,4 ;all done?
EXAMPLE 4-1: INDIRECT ADDRESSING goto NEXT ;NO, clear next
CONTINUE
· Register file 07 contains the value 10h
: ;YES, continue
· Register file 08 contains the value 0Ah
· Load the value 07 into the FSR register The FSR is a 5-bit wide register. It is used in
· A read of the INDF register will return the value conjunction with the INDF register to indirectly address
of 10h the data memory area.
· Increment the value of the FSR register by one The FSR<4:0> bits are used to select data memory
(FSR = 08) addresses 00h to 1Fh.
· A read of the INDR register now will return the
PIC12CE518: Does not use banking. FSR<6:5> are
value of 0Ah.
unimplemented and read as '1's.
Reading INDF itself indirectly (FSR = 0) will produce
PIC12CE519: Uses FSR<5>. Selects between bank 0
00h. Writing to the INDF register indirectly results in a
and bank 1. FSR<6> is unimplemented, read as '1' .
no-operation (although STATUS bits may be affected).
A simple program to clear RAM locations 10h-1Fh
using indirect addressing is shown in Example 4-2.
FIGURE 4-8: DIRECT/INDIRECT ADDRESSING
Direct Addressing Indirect Addressing
(FSR)
6 5 4 (opcode) 0 6 5 4 (FSR) 0
bank select location select bank location select
00 01
00h
Addresses
map back to
addresses
in Bank 0.
Data 0Fh
Memory(1) 10h
1Fh 3Fh
Bank 0 Bank 1(2)
Note 1: For register map detail see Section 4.2.
Note 2: PIC12CE519 only
DS40172A-page 18 Preliminary © 1997 Microchip Technology Inc.
PIC12CE5XX
5.0 PIC12CE518 I/O PORT 5.3 I/O Interfacing
As with any other register, the I/O register can be The equivalent circuit for an I/O port pin is shown in
written and read under program control. However, Figure 5-1. All port pins, except GP3 which is input
read instructions (e.g., MOVF GPIO,W) always read the only, may be used for both input and output
I/O pins independent of the pin's input/output modes. operations. For input operations these ports are non-
On RESET, all GPIO ports are defined as input (inputs latching. Any input must be present until read by an
are at hi-impedance) since the I/O control registers are input instruction (e.g., MOVF GPIO,W). The outputs are
all set. latched and remain unchanged until the output latch is
rewritten. To use a port pin as output, the
5.1 GPIO corresponding direction control bit in TRIS must be
GPIO is an 8-bit I/O register. Only the low order 6 bits cleared (= 0). For use as an input, the corresponding
are used (GP5:GP0) for pin control. Bits 6 and 7 (SDA TRIS bit must be set. Any I/O pin (except GP3) can be
and SCL) are used by the EEPROM peripheral. Refer programmed individually as input or output.
to Section 6.0 and Appendix A for use of SDA and FIGURE 5-1: EQUIVALENT CIRCUIT
SCL. Please note that GP3 is an input only pin. The FOR A SINGLE I/O PIN
configuration word can set several I/O's to alternate
Data
functions. When acting as alternate functions the pins Bus
will read as `0' during port read. Pins GP0, GP1, and D Q
GP3 can be configured with weak pull-ups and also Data
VDD
with wake-up on change. The wake-up on change and WR Latch
Port
weak pull-up functions are not pin selectable. If pin 4 is CK Q
P
configured as MCLR, weak pull-up is always on and
wake-up on change for this pin is not enabled.
W N I/O
5.2 TRIS Register Reg pin(1)
D Q
The output driver control register is loaded with the TRIS
VSS
contents of the W register by executing the TRIS f Latch
instruction. A '1' from a TRIS register bit puts the TRIS `f'
CK Q
corresponding output driver in a hi-impedance mode.
A '0' puts the contents of the output data latch on the
selected pins, enabling the output buffer. The Reset
exceptions are GP3 which is input only and GP2 which
may be controlled by the option register, see Figure 4-
5.
Note: A read of the ports reads the pins, not the
RD Port
output data latches. That is, if an output
driver on a pin is enabled and driven high, Note 1: I/O pins have protection diodes to VDD and VSS.
but the external system is holding it low, a
read of the port will indicate that the pin is
low.
The TRIS registers are "write-only" and are set (output
drivers disabled) upon RESET.
TABLE 5-1: SUMMARY OF PORT REGISTERS
Value on Va