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5 4 3 2 1
ZI5 SYSTEM BLOCK DIAGRAM
CPU CORE POWER
5V
3V
200/266/333MHZ
THERMAL DIODE IN
AMD Althon 64 2.5V DC/DC
H/W DDR ETC 19V IN
MONITOR P3 P3, 4
DIMM P27,28
D D
DDR POWER IN
DIMM Battery
2'nd FAN HyperTransport
P11 Link SMDDR_VTERM P12 Charger P29,30
CRT
P19
CK-GEN
ATI M10/M11 AGP BUS North Bridge ICS950405
P2 HOST CLOCK
TV-OUT
P19 INTA
VIA K8T800 DDR CLOCK
AGP CLOCK
PCI CLOCK
ETC MINI-PCI
P13, 14, 15,
LCD/INV P16, 17, 18 P5, 6, 7
C C
CONN P19
INTC/D
REQ2
V-LINK GNT2
AD20
266/533MB/s P24
HDD UltraDMA 100/133
P11
TI4510 1394
South Bridge CONN
CD-ROM P23
P11 VIA VT8235CE PCI BUS
INTB/C
REQ0 Slot0
USB 2.0 USB 2.0/1.1 GNT0
P8, 9, 10 AD18 P23
CONN P11
P23
B B
4-In-1 FIR Giga LAN
Card Reader
P22 SIO P20
RJ45
PC87393 P24
P20 LPT
MIC-IN INTB
P27 Port P22 REQ1
GNT1
AD22 P24
LINE-IN EXPEND
P27
AC97 AC'97 Link I/O
EC/KBC P22
Realtek Primary PC87570
Audio
HP-OUT Amplifier
ALC202 P21 LED/B
P27 G1421 P26 CONN
P22
P27
A A
Touch BIOS Keyboard FAN
RJ11 MDC PROJECT : ZI5
AC'97 Link Pad Quanta Computer Inc.
P22 P21 P20 P11
P24 Secondary
P26 Size Document Number R ev
Custom Block Diagram 1A
Date: Tuesday, March 30, 2004 Sheet 1 of 32
5 4 3 2 1
A B C D E
L79
DVCCLK
+3V
1
1
1
1
1
1
1
TI201209G121 C295 C300 C793 C260 C261 C299
4 4
C788 +
10U/10V-0805 .1U .1U .1U .1U .1U .1U
2
2
2
2
2
2
2
U28 APICCLK
R207 1 2 22 APICCLK (9)
2 1 FS0 R422 1 2 22 14M_SIO
VDDHTT *FS0/REF0 14M_SIO (19)
48 FS1 R400 1 2 22 OSCSB
REF1/*FS1 OSCSB (8)
35 45 FS2 R398 1 2 22 AC97_14M
VDDCPU REF2/*FS2 AC97_14M (25)
L42 38
AVCCLK VDDCPU VCLK0
+3V *MODEA/HTCLK0 6 R159 1 2 33 VCLK
VCLK (9)
9 7 GCLK_NB0 R419 1 2 33 GCLK_NB
VDDPCI *MODEB/PCI8/HTCLK1 GCLK_NB (6)
1
1
1
TI201209G121 C744 C743 C262 16 8 GCLK_AGP0R418 1 2 33 GCLK_AGP
VDDPCI PCI9/HTCLK2 GCLK_AGP (12)
C741 + 19 11
10U/10V-0805 .1U VDDPCI PCI11/HTCLK3
.1U
2
2
.1U 43 41 CPUCLK+0 R396
1 2 15 CPUCLK+
CPUCLK+ (3)
2
VDDA CPUCLKT0 CPUCLK-0 R395
CPUCLKC0 40 1 2 15 CPUCLK-
CPUCLK- (3)
29 AVDD48 CPUCLKT1 37
CPUCLKC1 36
46 VDDREF
CKGEN14M_I 3 13 SBPCLK0 R416 1 2 33 SBPCLK
X1 PCI0 SBPCLK (9)
CKGEN14M_O 4 ICS950405 14 PCMPCLK0 R415 1 2 33 PCMPCLK
X2 PCI1 PCMPCLK (22)
21 LPCPCLK0 R414 1 2 33 LPCPCLK
PCI4 LPCPCLK (19)
R407 *1M 44 22 LANPCLK0 R413 1 2 33 LANPCLK
RESET# PCI5 LANPCLK (23)
12 MINIPCLK0 R417 1 2 33 MINIPCLK
PCI10 MINIPCLK (24)
+3V R394 10K 32 17
Y2 *PD# 2XPCI2
2XPCI3 18
1
1
14.318MHZ SMDAT 26 23
(8,11) SMDAT SDATA 2XPCI6
C780 C758 SMCLK 25 24
(8,11) SMCLK SCLK 2XPCI7
3 10P 10P 3
2
2
5 31 FS3 R392 1 2 33 USBCLK
GND 48M/**FS3 USBCLK (7)
10 GND 24_48M/*SEL24_48# 28
15 GND
20 GND GND 34
27 * Internal PU 39
GND ** Internal PD GND
30 GND GND 42
33 GND GND 47
ICS950405
VCLK C798 1 2 *10P
GCLK_NB C795 1 2 *10P
+3V SBPCLK C297 1 2 *10P
GCLK_NB0 R420 10K PCMPCLK C296 1 2 *10P
VCLK0 R158 10K LPCPCLK C294 1 2 *10P
LANPCLK C293 1 2 *10P
MINIPCLK C298 1 2 *10P
Set Pin 7, Pin 8, Pin 9 to be HTCLK
USBCLK C742 1 2 *10P
2 2
CPUCLK HTT PCICLK
FS3 FS2 FS1 FS0 MHZ MHZ MHZ
0 0 0 0 100.90 67.27 33.63
0 0 0 1 133.90 66.95 33.48
0 0 1 0 168.00 67.20 33.60
0 0 1 1 202.00 67.33 33.67 +3V
0 1 0 0 100.20 66.80 33.40
0 1 0 1 133.50 66.75 33.38
0 1 1 0 166.70 66.68 33.34 R393 *10K FS3 R129 10K
0 1 1 1 200.40 66.80 33.40
1 0 0 0 150.00 60.00 30.00
1 0 0 1 180.00 60.00 30.00 R397 10K FS2 R130 *10K
1 0 1 0 210.00 70.00 35.00
1 0 1 1 240.00 60.00 30.00
1 1 0 0 270.00 67.75 33.75 R399 10K FS1 R131 *10K
1 1 0 1 233.33 66.67 33.33
1 1 1 0 266.67 66.67 33.33
1 1 1 1 300.00 75.00 37.50 R423 10K FS0 R421 *10K
1 1
PROJECT : ZI5
Quanta Computer Inc.
Size Document Number R ev
Custom CLOCK GENERATOR 1A
Date: Tuesday, March 30, 2004 Sheet 2 of 32
A B C D E
5 4 3 2 1
CPU H.T/CTL I/F
+1.2HT U4A +1.2HT_B0 U4C
AMD K8 AMD K8
LDT CTL & DBG
B27 V_HT0_A0 V_HT0_B0 AF25
B29 AE28 (5) -CPURST -CPURST AF20 A20 -SHDN
V_HT0_A1 V_HT0_B1 CPU_PWROK RESET# THERMTRIP#
C26 V_HT0_A2 V_HT0_B2 AF29 AE18 PWROK
C28 AG26 (5,9) -LDTSTOP -LDTSTOP AJ27 A26 THERMDA
V_HT0_A3 V_HT0_B3 HT_STOP# THERMDA THERMDC
D25 V_HT0_A4 V_HT0_B4 AG28 THERMDC A27
D27 AH27 L0_REF1 AF27
CADIP[0..15] V_HT0_A5 V_HT0_B5 CADOP[0..15] L0_REF0 L0_REF1
(5) CADIP[0..15] D29 V_HT0_A6 V_HT0_B6 AH29 CADOP[0..15] (5) AE26 L0_REF0 KEY0 AJ28 T54
D KEY1 A28 T53 D
CADIP15 T25 N26 CADOP15 COREFB+ A23 Near Socket754
CADIP14 HT_RXD15 HT_TXD15 CADOP14 COREFB- COREFB
U27 HT_RXD14 HT_TXD14 L25 A24 COREFB#
CADIP13 V25 L26 CADOP13 B23
HT_RXD13 HT_TXD13 T56 CORE_SENSE
CADIP12 W27 J25 CADOP12 AG18 CPU_CLK C19 3900P CPUCLK+ (2)
CADIP11 HT_RXD12 HT_TXD12 CADOP11 NC_BP3 R5
AA27 HT_RXD11 HT_TXD11 G25 T65 AE12 VDDIOFB NC_BP2 AH18
CADIP10 AB25 G26 CADOP10 AF12 AG17 BP1 169/F CPU_CLK- C18 3900P CPUCLK- (2)
HT_RXD10 HT_TXD10 T66 VDDIOFB# NC_BP1
CADIP9 AC27 E25 CADOP9 VDDIO_SENSE AE11 AJ18 BP0
CADIP8 HT_RXD9 HT_TXD9 CADOP8 VDDIO_SENSE NC_BP0 FBCLKOUT- R10 80.6/F FBCLKOUT
AD25 HT_RXD8 HT_TXD8 E26
CADIP7 T27 N29 CADOP7 CPU_CLK AJ21 AJ23 BPSCLK
CADIP6 HT_RXD7 HT_TXD7 CADOP6 CPU_CLK- CLKIN NC_BPSCLK BPSCLK-
V29 HT_RXD6 HT_TXD6 M28 AH21 CLKIN# NC_BPSCLK# AH23
CADIP5 V27 L29 CADOP5 VCC_CORE
CADIP4 HT_RXD5 HT_TXD5 CADOP4 FBCLKOUT
Y29 HT_RXD4 HT_TXD4 K28 AH19 FBCLKOUT NC_PLLCHZ AE24 T58
CADIP3 AB29 H28 CADOP3 FBCLKOUT- AJ19 AF24 R40 51.1/F COREFB+ COREFB+ (32)
HT_RXD3 HT_TXD3 FBCLKOUT# NC_PLLCHZ# T59
CADIP2 AB27 G29 CADOP2
CADIP1 HT_RXD2 HT_TXD2 CADOP1 SCANCLK1 R39 51.1/F COREFB-
AD29 HT_RXD1 HT_TXD1 F28 CPU_VCCA AH25 VDDA1 NC_SCANCLK1 D20 COREFB- (32)
CADIN[0..15] CADIP0 AD27 E29 CADOP0 CADON[0..15] AJ25 C21 SCANCLK2
(5) CADIN[0..15] HT_RXD0 HT_TXD0 CADON[0..15] (5) VDDA2 NC_SCANCLK2
D18 SCANEN
CADIN15 CADON15 NC_SCANEN SCANSHENB
R25 HT_RXD#15 HT_TXD#15 N27 NC_SCANSHENB C19
CADIN14 U26 M25 CADON14 VID0 AE15 B19 SCANSHENA +1.2HT_B0
HT_RXD#14 HT_TXD#14 (32) VID0 VID0 NC_SCANSHENA
CADIN13 U25 L27 CADON13 (32) VID1 VID1 AF15
CADIN12 HT_RXD#13 HT_TXD#13 CADON12 VID2 VID1 R295 44.2/F L0_REF1
W26 HT_RXD#12 HT_TXD#12 K25 (32) VID2 AG14 VID2 NC_RSVD_SCL D22 T61
CADIN11 AA26 H25 CADON11 (32) VID3 VID3 AF14 C22
HT_RXD#11 HT_TXD#11 VID3 NC_RSVD_SDA T60
CADIN10 AA25 G27 CADON10 (32) VID4 VID4 AG13 R293 44.2/F L0_REF0
C ADIN9 HT_RXD#10 HT_TXD#10 CADON9 VID4 BRN-
AC26 HT_RXD#9 HT_TXD#9 F25 NC_BRN# A19
C ADIN8 AC25 E27 CADON8
C ADIN7 HT_RXD#8 HT_TXD#8 CADON7 JP1
T28 HT_RXD#7 HT_TXD#7 P29 NC_DCLKTWO C15 T62
C ADIN6 U29 M27 CADON6 JTAG1 DBRDY AH17 +2.5V SHORT PAD
C ADIN5 HT_RXD#6 HT_TXD#6 CADON5 JTAG2 DBREQ- DBRDY SINCHN
V28 HT_RXD#5 HT_TXD#5 M29 AE19 DBREQ# NC_SINCHN C18
C ADIN4 W29 K27 CADON4 R13 680-0402 -CPURST 1 2
C ADIN3 HT_RXD#4 HT_TXD#4 CADON3 JTAG6 TMS
AA29 HT_RXD#3 HT_TXD#3 H27 E20 TMS
C ADIN2 AB28 H29 CADON2 JTAG7 TCK E17 AF21 K8_ANALOG0 R11 680-0402 -LDTSTOP
C C ADIN1 HT_RXD#2 HT_TXD#2 CADON1 JTAG4 TRST- TCK NC_ANALOG0 K8_ANALOG1 R44 680-0402 -SHDN Must shut down when asserted C
AC29 HT_RXD#1 HT_TXD#1 F27 B21 TRST# NC_ANALOG1 AF22
C ADIN0 AD28 F29 CADON0 JTAG5 TDI A21 AF23 K8_ANALOG2
HT_RXD#0 HT_TXD#0 JTAG3 TDO TDI NC_ANALOG2 K8_ANALOG3 R46 680-0402 BRN-
A22 TDO NC_ANALOG3 AE23
(5) CLKIP1 CLKIP1 Y25 J26 CLKOP1 CLKOP1 (5) R47 680-0402 SINCHN
CLKIP0 HT_RXCLK1 HT_TXCLK1 CLKOP0 R15 680-0402 DBRDY
(5) CLKIP0 Y27 HT_RXCLK0 HT_TXCLK0 J29 CLKOP0 (5)
A25 K1 R14 680-0402 DBREQ-
CLKIN1 CLKON1 NC_A25 NC_K1
(5) CLKIN1 W25 HT_RXCLK#1 HT_TXCLK#1 J27 CLKON1 (5) B7 NC_B7 NC_R2 R2
(5) CLKIN0 CLKIN0 Y28 K29 CLKON0 CLKON0 (5) B13 R3 1 2 TMS
HT_RXCLK#0 HT_TXCLK#0 NC_B13 NC_R3 SCANCLK2
B18 NC_B18 NC_AA2 AA2 3 4
CTLIP1 R27 N25 CTLOP1 C1 AA3 5 6 TRST-
HT_RXCTL1 HT_TXCTL1 T57 NC_C1 NC_AA3
(5) CTLIP0 CTLIP0 T29 P28 CTLOP0 CTLOP0 (5) C3 AE9 7 8 TDI
HT_RXCTL0 HT_TXCTL0 NC_C3 NC_AE9 RP5 680-8P4R
C6 NC_C6 NC_AE21 AE21
CTLIN1 R26 P25 CTLON1 C9 AE22 Rev F modify 2.5VSUS
HT_RXCTL#1 HT_TXCTL#1 T55 NC_C9 NC_AE22
(5) CTLIN0 CTLIN0 R29 P27 CTLON0 CTLON0 (5) C20 AG2
HT_RXCTL#0 HT_TXCTL#0 NC_C20 NC_AG2 R41 680-0402 TDO
C23 NC_C23 NC_AG4 AG4
C24 NC_C24 NC_AG6 AG6
D3 AG7 R17 51.1/F VDDIO_SENSE
NC_D3 NC_AG7
F3 NC_F3 NC_AG9 AG9
J3 AH1 2.5VSUS
NC_J3 NC_AH1