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5 4 3 2 1
D D
Inventec Corporation
R&D Division
C C
CONFIDENTIAL
B B
Board name : Mother Board Schematic
A A
Project : xxxx (FSC_v5535)
Inventec Corporation
Version : 01
5F, No. 35, Section 2, Zhongyang South Road
Beitou District, Taipei 11270, Taiwan
TEL:+886-2-2881-0721
Title
Initial Date : April ,7 , 2007 Size
Title
Document Number
Custom
Rev
A02
Date: Friday, June 15, 2007 Sheet 1 of 31
5 4 3 2 1
5 4 3 2 1
1. Schematic Page Description :
Schematic Ver : 01
D
01. Title 21. KBC-ITE-8512
D
02. Schematic Page Description 22. AUDIO ALC268/AMP
03. Block Diagram 23. Audio JACK
04. ANNOTATIONS 24. 5VA/5VLA/3VA/3VLA
05. Schematic Modify 25. 5/3VS/1.5VA/1.5VS/VCCP
06. Power Block Diagram 26. DDR POWER (TPS51117)/1.8VA/1.8VS
07. Yonath Processor (1/2) 27. 1.2VA/1.2VS
08. Yonath Processor (2/2) 28. CPU Core Power (MAX8770)
09. Clock Generator(ICS9PR600DGLFT) 29. AC-IN & BATT POWER
10. SIS672MX (1/2) 30. USB BOARD
11. SIS672MX (2/2) 31. GP S/W BOARD
12. DDRII-DIMM 0-1
13. SiS307LV
C C
14. CRT& LCD
15. SiS 968 (1/3)
16. SiS 968 (2/3)
17. SiS 968 (3/3)
18. LAN (SiS196) & MDC
19. HDD & CDROM
20. 3G/Mini/New card
B B
A A
Inventec Corporation
5F, No. 35, Section 2, Zhongyang South Road
Beitou District, Taipei 11270, Taiwan
TEL:+886-2-2881-0721
Title
Size
Schematic Page Description
Document Number Rev
Custom A02
Date: Friday, June 15, 2007 Sheet 2 of 31
5 4 3 2 1
5 4 3 2 1
3. Block Diagram :
CLK Gen.
ICS9LPR600D
P.9
D D
CPU CPU-166MHz/133MHz+/-x2
Thermal Intel CORE
MAX8770
ZCLK-133MHz+/-
100MHz+/- x6
x1
Sensor P.28 48MHz x1
ADM1032AR Yonath 33MHz x6
P.8 14MHz x1
CPU 12MHz x1
Processor VCCP
P.7-8 P.25
Host Bus
CRT SiS Mem Bus
DDR2 667
P.14 INTERFACE
SiS M672 P.12
LCD 307LV 847-Balls With
P.14 167-Balls Integrated SiS MirageTM 3 GUI 2D/3D Graphic,
C
13x13 mm 35x35 mm 1 GB/s Multithread I/O Link,
C
BGA
P.13
TEBGA 4 GB/s 16 Lane PCI-Express Graphic Port, and
P.10-11
Mini Card (3G) 5.3 GB/s Single DDR2-667 Channel
For Pentium M PC Systems
P.20 Hub Interface
LAN Phy Audio HEADPHONE
RJ-45 SiS 196 AC'97 AMP P.22
P.18
64 pin LQFP
SiS IDE BUS CDROM
P.19 CODEC
P.23
P.18
968 ALC268
Mic IN
Express Card 570-Balls SATA BUS HDD P.22 P.23
P.20 27x27 mm P.19
TEBGA AC-Link MDC CNN
USB 2.0 P.15-17 P.18
Mini Card
(WLAN) P.20 USB-2 P.15 USB-1 P.15 USB-0 P.15
B B
LPC BUS
ITE
IT8512E RESET
P.21 P.21
FAN CNN
P.8
RTC SPI 8M ROM
P.15 P.21
A A
Inventec Corporation
5F, No. 35, Section 2, Zhongyang South Road
Beitou District, Taipei 11270, Taiwan
TEL:+886-2-2881-0721
Title
Size
Block Diagram
Document Number Rev
Custom A02
Date: Friday, June 15, 2007 Sheet 3 of 31
5 4 3 2 1
5 4 3 2 1
4. Nat name Description : Power Rail
VCC_CORE
Destination
Merom HFM:
Voltage
1.3319V~1.4375V~1.4591V 36A
S0 Current
LFM: 0.9221V~0.9625V~0.9739V
+1.05VS Merom: AGTL+ termination 0.997V~1.05V~1.102V 2.5A
SIS762 1.0V~1.05V~1.1V 80mA
Voltage Rails SIS968 22mA
DCIN Primary DC system power supply SIS762 1.7V~1.8V~1.9V 664mA
D
5VLA 5.0V always on power rail by LATCH or ACIN +1.8V D
3VLA 3.0V always on power rail by LATCH or ACIN SO-DIMM: 4.0A
5VA 5.0V always on power rail by ECPWON 0.9VDDT_DDRII:
DDRII Terminator: 0.855V~0.9V~0.945V 1.0A
3VA 3.3V always on power rail by ECPWON
1.8VA 1.8V always on power rail 1.2VS SIS968 2.69A
1.5VA 1.5V always on power rail +1.5VS Merom PLL 1.425V~1.5V~1.575V 120mA
1.2VA 1.2V always on power rail
Mini Card: WirelessLan 500mA
5VS 5.0V switched power rail by SLP_S3# Express Card: 650mA
3VS 3.3V switched power rail by SLP_S3#
1.8VS 1.8V switched power rail by SLP_S3# SIS762 600mA
1.5VS 1.5V switched power rail by SLP_S3# 1.8VS
1.2VS 1.2V switched power rail by SLP_S3# SIS968 816mA
SIS307ELV 389mA
1.8V 1.8V DDR Voltage
+V0.9_DDR 0.9V DDR Termination Voltage SIS968 3.135V~3.3V~3.465V 74mA
3VS
Vccp AGTL+ Voltage for CPU LCD: 3.0V~3.3V~3.6V 1.5A
Vcore_CPU Core Voltage for CPU Mini Card: UMTS 600mA
Express Card: 1.3A
C 2.5V (LAN) 2.5V power rail for LAN CLK Generator: ICS9LPRS365AGLF 3.135V~3.3V~3.465V 400mA
C
Part Naming Conventions Mini Card: WirelessLan 1.0A
C = Capacitor
CN = Connector Azalia Codec: ALC268 3.0V~3.3V~3.6V
25mA
D = Diode Azalia MDC:
30mA
F = Fuse HDD: SATA
L = Inductor LED: 3.0V~3.3V~3.6V 60mA
Q = Transistor SIS307ELV 132mA
R = Resistor
RS = Resistor Pack 5VS
LED: 140mA
U = Arbitrary Logic Device Azalia Codec: ALC268 3.0V~3.3V~3.6V 35mA
Y = Crystal and Osc FAN:
HDD: SATA 4.75V~5.0V~5.25V Max: 1.0A ; R/W: 460mA ; STDBY: 70mA
ODD: PATA 4.75V~5.0V~5.25V Max: 1.8A ; R/W: 900mA ; STDBY: 45mA
Audio AMP: G1432
Net Name Suffix Inverter: 1.34A
B
0 or # = Active Low signal 1.2VA SIS762 69mA
B
1.5VA SIS196 393mA
23mA
SIS762
1.8VA 327mA
SIS968
2.5VA SIS196 2.32V~2.5V~2.625V 223mA
Thermal Sensor:
+3VA SIS968 8mA
5.Board Stack up Description SIS968: RTC
Express Card: 275mA
+5VA USB: x 3 ports 5VA 1.5A
PCB Layers PCB Thickness :1.2mm+/-0.1 mm . 3VLA EC: ITE8512F
Layer 1 Component Side, Microstrip signal Layer
+5VLA Control Power
A
Layer 2 Power Plane A
Layer 3 Stripline Layer(AGTL,CLOCK,DDR)
Inventec Corporation
5F, No. 35, Section 2, Zhongyang South Road
Beitou District, Taipei 11270, Taiwan
TEL:+886-2-2881-0721
Layer 4 Stripline Layer(Analog,LVDS,other)
Title
Layer 5 Ground Plane ANNOTATIONS
Size Document Number Rev
Custom A02
Layer 6 Solder Side,Microstrip signal Layer
Date: Friday, June 15, 2007 Sheet 4 of 31
5 4 3 2 1
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6.Schematic modify Item and History :
release version 0.2
1.REMOVE R471,C584,C586,R450,R449,R359,R92,R365
2.R439 PULL DOWN
3.L57 MODIFY
4.R459 modify-->7.5k
D 5.ADD R553 D
6.R301 ---modify 10k
7.C418,R311 NU
8.R312 MODIFY---220K
9.BATIN MODIFY TO PIN 17
10.ADD C1107
11.F1 MODIFY TO 5A
12.R309 MODIFY 10K
13.MODIFY L57,L56 TO SIZE6*6*3
C C
B B
A A
Inventec Corporation
5F, No. 35, Section 2, Zhongyang South Road
Beitou District, Taipei 11270, Taiwan
TEL:+886-2-2881-0721
Title
Size
Schematic Modify
Document Number Rev
Custom A02
Date: Friday, June 15, 2007 Sheet 5 of 31
5 4 3 2 1
5 4 3 2 1
SYSTEM POWER ON/OFF SEQUENCE
Power on/off sequence AC insert(First) Battery only Power on/off sequence Suspend resume sequence(S3)
Power on sequence Power off sequence Power on sequence Power off sequence
Power on sequence Power off sequence
RTCVCC RTCVCC RTCVCC
5VLA/3VLA 5VLA/3VLA 5VLA/3VLA
D D
5VAUXON 5VAUXON 5VAUXON
EC_3VLA
EC_3VLA EC_3VLA
SW OFF:
SW OFF: SW OFF:
PWR_SWIN#
PWR_SWIN# PWR_SWIN#
LATCH_ON
5VA must be powered up before 3VA, or after 3VA within 0.7V LATCH_ON LATCH_ON
3VA,5VA 5VA must be powered up before 3VA, or after 3VA within 0.7V
10ms 3VA,5VA 3VA,5VA
10ms
2.5VA,1.8VA,1.5VA,1.2VA
2.5VA,1.8VA,1.5VA,1.2VA 2.5VA,1.8VA,1.5VA,1.2VA
AUX_PERGD
AUX_PERGD AUX_PERGD
SW ON:
SW ON: SW ON:
PWR_BTN#
PWR_BTN# PWR_BTN#
PSON#
PSON# PSON#
S3AUXSW#
S3AUXSW# S3AUXSW#
SUSB#
SUSB# SUSB#
SUSC#
SUSC# SUSC#
C C
1.8V
1.8V 1.8V
5VS,3VS
5VS,3VS 5VS,3VS
1.2VS,1.5VS,1.8VS
1.2VS,1.5VS,1.8VS 1.2VS,1.5VS,1.8VS
0.9VS_DIMM
0.9VS_DIMM 0.9VS_DIMM
1.2VS_PWRGD
1.2VS_PWRGD 1.2VS_PWRGD
+VCCP
+VCCP +VCCP
VCCP_POK
VCCP_POK VCCP_POK
VCORE_GOOD
VCORE_GOOD VCORE_GOOD
SYS_GOOD
SYS_GOOD SYS_GOOD
PCI_RST#
PCI_RST# PCI_RST#
B B
A A
Inventec Corporation
5F, No. 35, Section 2, Zhongyang South Road
Beitou District, Taipei 11270, Taiwan
TEL:+886-2-2881-0721
Title
Size
Power Block Diagram
Document Number Rev
Custom A02
Date: Friday, June 15, 2007 Sheet 6 of 31
5 4 3 2 1
5 4 3 2 1
System Bus Common Clock Signal Layout Guide :
ADS# , BNR# , BPRI# , BR0# , DBSY# , DEFER# , DPWR# , DRDY# , HIT# , HITM# , LOCK# ,
AGTL+_HA0[31..3] RS[2..0]# , TRDY# , RESET#.
{10} AGTL+_HA0[31..3]
Transmission Line Type Total Trace Length Normal Impedance Spacing (mils)
U28A Strip-line(Int. Layer) 1.0 ~ 6.5 inch 55+/-10% 4 & 8(Int. Layer)
AGTL+_HA03 J4 H1 AGTL+_ADS# Micro-strip(Ext. Layer) 5 & 10(Ext. Layer)
A[3]# ADS# AGTL+_ADS# {10}
AGTL+_HA04 L4 E2 AGTL+_BNR#
A[4]# BNR# AGTL+_BNR# {10}
AGTL+_HA05 M3 G5 AGTL+_BPRI#
A[5]# BPRI# AGTL+_BPRI# {10}
AGTL+_HA06 K5 A[6]#
ADDR GROUP 0
AGTL+_HA07 M1 H5 AGTL+_DEFER#
AGTL+_HA08 N2
A[7]# DEFER#
F21 AGTL+_DRDY#
AGTL+_DEFER# {10} Source Synchronous DATA :
A[8]# DRDY# AGTL+_DRDY# {10}
AGTL+_HA09 J1 E1 AGTL+_DBSY# DATA#[63..0] , DINV#[3..0] , DSTBN#[3..0] , DSTBP#[3..0]
A[9]# DBSY# AGTL+_DBSY# {10}
AGTL+_HA010 N3
AGTL+_HA011 A[10]# AGTL+_BR0#
AGTL+_HA012
P5 A[11]# BR0# F1 AGTL+_BR0# {10} Transmission Line Type Total Trace Length Normal Impedance Spacing (mils)
P2
CONTROL
AGTL+_HA013 A[12]# IERR#
D L1 A[13]# IERR# D20 Strip-line 1.0 ~ 5.5 inch 55+/-10% 4 & 12 D
AGTL+_HA014 P4 B3 CPU_INIT#
A[14]# INIT# CPU_INIT# {15}
AGTL+_HA015 P1
AGTL+_HA016 A[15]# AGTL+_LOCK#
AGTL+_ADSTB00
R1 A[16]# LOCK# H4 AGTL+_LOCK# {10} Signals Name Signals Matching Strobes associated Strobe Matching
{10} AGTL+_ADSTB00 L2 ADSTB[0]#
RESET# B1 AGTL+_CPURST#
AGTL+_CPURST# {10}
with the group
AGTL+_HREQ00 K3 F3 AGTL+_RS00 DATA#[15..0] , DINV0# +/- 100 mils DSTBP0#,DSTBN0# +/- 25 mils
REQ[0]# RS[0]# AGTL+_RS00 {10}
AGTL+_HREQ01 H2 F4 AGTL+_RS01
REQ[1]# RS[1]# AGTL+_RS01 {10}
AGTL+_HREQ02 K2 G3 AGTL+_RS02 DATA#[31..16] , DINV1# +/- 100 mils DSTBP1#,DSTBN1# +/- 25 mils
REQ[2]# RS[2]# AGTL+_RS02 {10}
AGTL+_HREQ03 J3 G2 AGTL+_TRDY#
REQ[3]# TRDY# AGTL+_TRDY# {10}
AGTL+_HREQ04 L5 DATA#[47..32] , DINV2# +/- 100 mils DSTBP2#,DSTBN2# +/- 25 mils
REQ[4]# AGTL+_HIT#
{10} AGTL+_HREQ0[4..0] HIT# G6 AGTL+_HIT# {10}
AGTL+_HA017 Y2 E4 AGTL+_HITM# DATA#[63..48] , DINV3# +/- 100 mils DSTBP3#,DSTBN3# +/- 25 mils
A[17]# HITM# AGTL+_HITM# {10}
AGTL+_HA018 U5
AGTL+_HA019 A[18]# BPM00
R3 A[19]# BPM[0]# AD4
ADDR GROUP 1
AGTL+_HA020 W6 AD3 BPM01
AGTL+_HA021 A[20]# BPM[1]# BPM02
U4 AD1