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5 4 3 2 1
Project code: 91.4CE01.001
PCB P/N : 48.4CE01.0SC
REVISION : 08255-SC
DDR2 667/800MHz
PCB STACKUP SYSTEM DC/DC
AMD Giffin CPU TPS51125 49
D 667/800 MHz
16,17 G792 TOP
INPUTS OUTPUTS
D
S1G2 (35W) 39 VCC
DCBATOUT
5V_S5(7A)
DDR2 638-Pin uFCPGA638 S
3D3V_S5(7A)
667/800MHz 4,5,6,7 SYSTEM DC/DC
667/800 MHz
16,17 S TPS51124 50
CRT
22 GND INPUTS OUTPUTS
OUT
1D1V_S0(8A)
IN
16X16 BOTTOM DCBATOUT
CLK GEN. LCD 1D2V_S0(5A)
21
ICS ICS9LPRS480 SYSTEM DC/DC
3 North Bridge HDMI TPS51117 52
AMD RS780M 23 INPUTS OUTPUTS
Line In CPU I/F LVDS, CRT I/F
DCBATOUT 1D8V_S3(10A)
INTEGRATED GRAHPICS PCIex16
34 Codec AZALIA RT9026PFP 51
MXM3.0 DDR_VREF_S3
C ALC888S 19 1D8V_S3 C
MIC In 31 8,9,10 0D9V_S3(1A)
34 RT9166 51
Line Out(SPDIF) A-Link
LAN
Giga LAN TXFM RJ45 3D3V_S0
2D5V_S0
(300mA)
30 30
4X4 BCM5784MKMLG 29 G957 51
34 OP AMP
3D3V_S0 1D5V_S0(1A)
G1412R 32 New card PWR SW
W83L351 38 G9161(UMA) 51
South Bridge 38 1D2V_S5
Front.SPKR 3D3V_S5
AMD SB700
PCIex1 (400mA)
OP AMP Mini Card G9131(DIS) 51
34 Kedron a/b/g/n 37
USB 2.0 12 ports 1D2V_S5
G1454R 32 3D3V_S5 (300mA)
USB 1.1 2 ports
Mini Card
ETHERNET (10/100/1000Mb) TV tuner 37
SUBWOOFER CHARGER
High Definition Audio MAX8731A 53
ATA 66/100 CardReader SD/MMC/MS/
B
33 OP AMP USB INPUTS OUTPUTS
B
G1442R 32 ACPI 1.1 AU6433 MS PRO/XD
5 in 1
LPC I/F
36 36
CHG_PWR
18V 6.0A
PCI/PCI BRIDGE DCBATOUT
MODEM LPC BUS UP+5V
11,12,13,14,15
RJ11 MDC Card 5V 100mA
35 BIOS
USB Winbond CPU DC/DC
W25X80 ISL6265HR 48
SATA KBC 41 LPC INPUTS OUTPUTS
Mini USB Camera
Winbond DEBUG VCC_CORE_S0_0
WPC773L Launch CONN.41
Blue Tooth 27 21 40 0~1.55V 18A
USB I Button
42 VCC_CORE_S0_1
26 DCBATOUT
0~1.55V 18A
Finger USB II VDDNB
HDD SATA I Printer 43 4 Port 28 Touch INT. CIR
Pad 43 KB 40 0~1.55V 18A
A 24 41 A
ODD SATA Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
25
Title
HDD SATA II
BLOCK DIAGRAM
Size Document Number Rev
24 A3
JM70-PU -2
Date: Monday, March 02, 2009 Sheet 1 of 56
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
HISTORY
Size Document Number Rev
A3 JM70-PU -2
Date: Monday, March 02, 2009 Sheet 2 of 56
5 4 3 2 1
5 4 3 2 1
090206 -1
090119 -1
3D3V_S0 3D3V_CLK_VDD
3D3V_S0
DY
1 R115 2 R131
0R0603-PAD 1 2 3D3V_48MPW R_S0
1
1
1
1
1
1
1
1
1
C186 C187 C610 C585 C597 C606 C580 C223 C571 Due to PLL issue on current clock chip, the SBlink clock
SC4D7U6D3V3KX-GP
1
1
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
2R3J-GP C235 C619
SC1U10V2KX-1GP need to come from SRC clocks for RS740 and RS780.
DY DY
2
2
2
2
2
2
2
2
2
3000mA.80ohm Future clock chip revision will fix this.
2
2
D D
Clock chip has internal serial terminations
090119 -1 for differencial pairs, external resistors are
3D3V_S0
reserved for debug purpose.
1 R132 2 090206 -1
0R0603-PAD
1D1V_S0 1D1V_CLK_VDDIO
R306 DY C622
1 DY 2 R343 SC33P50V2JN-3GP
1 DY 2 2 1
1
1
1
1
1
1
1
0R3-0-U-GP C216 C578 C583 C202 C572 C575 C607 3D3V_CLK_VDD X5
2
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
10MR2J-L-GP X-14D31818M-44GP
DY DY U46
2
2
2
2
2
2
2
1D1V_CLK_VDDIO 82.30005.951
26 61 GEN_XTAL_IN 2ND = 82.30005.A41 C623 090213 -1
1
VDDATIG X1 GEN_XTAL_OUT
25 VDDATIG_IO X2 62 2 1
CL=20pF